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As I struggled today with an FPGA CAD tool's IP code generation and management, it occurred to me that I haven't needed to write HDL-generating code for years now. Extreme modularization, along with generate blocks and parameters, has always sufficed, even for 20k+ line designs.

submitted 46 days ago • 2 comments

Bit twiddling hacks are "neat tricks" in software, but they are often branch-free and need no allocated memory, so they map naturally to hardware design. More listed here: fpgacpu.ca/fpga/reading...

submitted 91 days ago • 0 comments

Here is a module which extends the 1-to-N Differential Deserializer by packing two consecutive differential N-bit deserialized words into one differential 2N-bit word and extending the bitslip word-alignment logic to support this double-width word. fpgacpu.ca/fpga/Deseria...

submitted 161 days ago • 0 comments

When aligning multiple data channels, you need to pass them through variable-delay shift registers. This is where using an FPGA's built-in shift-register hardware is a must, since using LUTs+FFs ends up being the large majority of the deserializer area! fpgacpu.ca/fpga/Registe...

submitted 166 days ago • 0 comments

A pipeline serial to parallel converter. Reads in multiple serial words and signals when the last input word has been read-in and a new, wider output word is ready to be read-out, in the same cycle if necessary to receive an uninterrupted serial stream. fpgacpu.ca/fpga/Pipelin...

submitted 168 days ago • 0 comments

A deserializer for differential data, with a configurable 1:N ratio, SDR or DDR data rate, and independent positive and negative data polarity input delays and deserializers, which enable bit and word alignment training later on. fpgacpu.ca/fpga/Deseria...

submitted 174 days ago • 0 comments

An IDELAYCTRL instance for calibrating IDELAY2 blocks. This is the first step to high-speed interfaces on Series 7 AMD/Xilinx FPGAs. fpgacpu.ca/fpga/IDELAYC...

submitted 179 days ago • 0 comments

fpgacpu.ca now supports HTTPS! It's still a static site without cookies or Javascript or any inputs, but I was getting reports of problems with browsers, corporate networks, and Google not liking the absence of SSL. Enjoy more easily now!

submitted 179 days ago • 0 comments

I have an open slot for a client at this time. Let's discuss your FPGA design needs! fpgacpu.ca/gateforge/in... I'm a consultant doing primarily logic design on FPGAs and related full-stack software development for clients who need application-specific processing for their products.

submitted 188 days ago • 0 comments

I have an open slot for a client, starting immediately. Let's discuss your FPGA design needs! fpgacpu.ca/gateforge/in... I'm a consultant doing primarily logic design on FPGAs and related full-stack software development for clients who need application-specific processing for their products.

submitted 208 days ago • 0 comments

In one project, I had to first configure an external device before it could generate it's own source-synchronous clock for data and control. This Clock Switchover module detects when the device data clock becomes active and stable and handles clock selection and reset. fpgacpu.ca/fpga/Clock_S...

submitted 262 days ago • 0 comments

I have an open slot for a client, starting in the last week of July. Let's discuss your needs! fpgacpu.ca/gateforge/in... I'm a consultant doing logic design on FPGAs and related software development (from kernel up to application) for clients who need application-specific processing.

submitted 263 days ago • 0 comments

We can now build a saturating accumulator with variable upper/lower limits. I used this as the Integral term of a PID controller, where the limits are dynamically adjusted to limit integral wind-up, which makes the PID controller recover from saturation faster. fpgacpu.ca/fpga/Accumul...

submitted 263 days ago • 0 comments

Here's a Saturating Adder/Subtractor. The limits can be any signed numbers, even dynamically variable. One use is as the final stage of a PID controller, so we can guarantee the output never wraps around and flips sign suddenly, which would be catastrophic. fpgacpu.ca/fpga/Adder_S...

submitted 265 days ago • 0 comments

With an Subtractor that provides the carry-out and the overflow, we can create an Arithmetic Predicates module which computes all possible signed and unsigned comparisons of two numbers. This way we don't have to worry about getting RTL arithmetic right each time. fpgacpu.ca/fpga/Arithme...

submitted 266 days ago • 0 comments

And with those previous modules, we can now build an adder/subtractor module. It's much more complex than usual, but it also gives us all bit carries and the overflow bit, and is independent of Verilog's signed/unsigned arithmetic behaviour. fpgacpu.ca/fpga/Adder_S...

submitted 269 days ago • 0 comments

Next step in getting to saturating arithmetic: a Binary Carry-In calculator, which tells us which bits in a sum had a carry-in, which has many uses (overflow, predicates, vector registers, etc...) fpgacpu.ca/fpga/CarryIn...

submitted 270 days ago • 0 comments

Let's build up to some saturating arithmetic logic. Here's a Width Adjuster, which either extends (optionally signed) or truncates values. I often use it to normalize widths of misc. signals before packing/unpacking/multiplexing/arithmetic/etc... fpgacpu.ca/fpga/Width_A...

submitted 271 days ago • 0 comments

Here's a Pipeline Credit Gate. It let's handshakes complete only if there are available credits, which are added via external pulses and subtracted by each completed handshake. It can ensure that an operation is only considered complete after N items have been read out. fpgacpu.ca/fpga/Pipelin...

submitted 273 days ago • 0 comments

I've updated my "rules for ready/valid handshakes" to describe both a control implementation I made heavy use of in the past year, and to add discussion on the synchronization operation which underlies ready/valid handshakes, much like ready/valid handshakes underlie AXI4. fpgacpu.ca/fpga/handsha...

submitted 276 days ago • 0 comments

A Handshake Multiplier, which accepts and buffers the command, and will not accept a new command until the buffered copy has been accepted a set number of times (specified in the command) by the internal module. fpgacpu.ca/fpga/Pipelin...

submitted 277 days ago • 0 comments

I built myself a little linter out of Verilator, Icarus, and some greps. It finds all the little width mismatches, any combinational loops, typos, missing ports, etc... It's a LOT faster than synthesis, and nearly eliminates CAD warnings, making finding bugs later easier. fpgacpu.ca/fpga/verilin...

submitted 285 days ago • 0 comments

When writing very modular HDL code the module instantiations become the bulk of the program. Here is a script, not a real parser just a quick hack, which reads just the start of one of my Verilog modules and spits out a roughly formatted blank instantiation template. fpgacpu.ca/fpga/generat...

submitted 286 days ago • 0 comments

In theory, any combinational path between ready and valid should be avoided. In practice, that can bloat a design with skid buffers, and misses out on some useful control logic (like that Synchronizer). Some combinational ready/valid paths are acceptable, with care. fpgacpu.ca/fpga/handsha...

submitted 290 days ago • 0 comments

My favourite thing about elastic pipelines is how they distribute control. A Pipeline Synchronizer forces all inputs to only accept new inputs simultaneously. Thus a faster input is modulated without having to touch the central control logic. fpgacpu.ca/fpga/Pipelin...

submitted 291 days ago • 0 comments

Since I got asked about documentation yesterday, here's the Python script I use: It takes Verilog code and processes the comments (line comments only) as Markdown, and wraps the code in <pre> blocks. This generates a quick, neat HTML page that uses any CSS you want for style. fpgacpu.ca/fpga/v2h.py

submitted 292 days ago • 0 comments

Let's have a look at the guts of the CDC FIFO buffer. The nucleus is the ability to pass the read and write addresses across clock domains. I do it via toggle signals, which allows non-sequential addresses. This also means we are not limited to power-of-2 buffer depths. fpgacpu.ca/fpga/CDC_Wor...

submitted 293 days ago • 0 comments

Following up on the CDC FIFO Repacker: it is a specialization of this plain CDC FIFO Buffer. The main difference is the number of counters used to track where the data begins and end. It also does CDC of whole words without using Grey Codes. :) fpgacpu.ca/fpga/CDC_FIF...

submitted 294 days ago • 0 comments

Here's a CDC FIFO Repacker, a hardware module to pack/unpack arbitrary data without stalls and without introducing gaps in the data words, while crossing clock domains. The tradeoff I made here was to sacrifice area for simplicity and speed. fpgacpu.ca/fpga/CDC_FIF...

submitted 297 days ago • 0 comments

If a memory has dual use, the data sizes for each use case may not match. You can pre-compute the Least Common Multiple of the data sizes to make sure either use case can store an integer number of items. This simplifies addressing and multiplexing. (more on this later...) fpgacpu.ca/fpga/lcm_fun...

submitted 298 days ago • 0 comments

When you focus on synthesizable-only Verilog like I do, it's easy to forget that you can do arbitrary computations during elaboration to compute constants for synthesis. Here's an example: a helper function to compute the Greatest Common Divisor of two integers. fpgacpu.ca/fpga/gcd_fun...

submitted 300 days ago • 0 comments

For analog, there is Spice. It's hard to use, and fails to simulate in obscure ways. I'm a fan of CircuitJS1, which is so interactive, and portable: github.com/sharpie7/cir... And I just discovered CircuitShepherd, which is even more amazing (though for iOS/Mac only): www.circuitshepherd.com

submitted 311 days ago • 0 comments

Someone asked "what application areas within FPGA design have the most potential for consulting opportunities?" I've seen two primary application areas in my FPGA consulting practice. One is ordinary. One is esoteric. People usually need one or both when they need an FPGA.

submitted 322 days ago • 1 comment

A sketch of a fourth-order low-pass filter circuit using plain RLC design with floating gyrators to synthesize the inductors. This design makes LPFs easier to calculate. Floating gyrators enables many other active filter circuits not normally feasible. fpgacpu.ca/bass/floatin...

submitted 334 days ago • 0 comments

A fourth-order high-pass filter circuit. However, instead of the usual multiple-feedback or Sallen-Key designs I use a plain RLC design with conventional grounded gyrators to synthesize the inductors. An RLC filter's parameters are very easy to calculate. fpgacpu.ca/bass/gyrator...

submitted 334 days ago • 0 comments

When I look at the logs on my website, the clog2() Verilog-2001 function is the most searched query. This implementation deals with a quirk of Vivado to reduce warnings. It's useful to compute address and counter widths from other parameters. fpgacpu.ca/fpga/clog2_f...

submitted 341 days ago • 0 comments

I am currently in negotiations to fill my two open slots for new FPGA design clients. These will fill fast. Let's discuss your needs! fpgacpu.ca/gateforge/in...

submitted 342 days ago • 0 comments

I normally post about digital logic, but when I looked for analog circuits to generate only even harmonics, I couldn't find any. So I designed one. It's simple, but tricky: any extra non-linearity will add odd harmonics. If there is another solution, please let me know. fpgacpu.ca/bass/even_ha...

submitted 346 days ago • 0 comments

I'm writing an online book: "FPGA Design Elements", which provides a reference library of fundamental digital logic design elements. Think of it as a hardware analog to the C Standard Library ("libc") and its documentation. fpgacpu.ca/fpga/index.h... github.com/laforest/FPG... #FPGA

submitted 346 days ago • 0 comments